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| - 1 - K9F2G08U0C rev. 0.2, may. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2010 samsung electronics co., ltd. all rights reserved. advance 2gb c-die nand flash single-level-cell (1bit/cell) datasheet free datasheet http://www.datasheetlist.com/
- 2 - datasheet flash memory rev. 0.2 K9F2G08U0C advance revision history the attached data sheets are prepared and approved by samsung el ectronics. samsung electronics co., ltd. reserve the right to c hange the specifications. samsung electr onics will evaluate and reply to your requests and questions ab out device. if you have any questi ons, please contact the samsung branch office near your office. revision no. history draft date remark editor 0.0 1. initial issue aug. 12, 2009 advance - 0.1 1. dc parameter is chagned 2. typo is modified dec. 09, 2009 advance - 0.2 1. max tr value has changed from 35us to 40us 2. min trc/ twc value has changed from 30ns to 25ns 3. chapter 2.9, 2.10 ac parameters revised 4. chapter 2.3 isb2 max value has changed from 50 to 80 5. chapter 7.0 2plane erase not supported. 6. chapter 2.8 tdbsy value has changed. may. 03, 2010 advance h.k.kim free datasheet http://www.datasheetlist.com/ - 3 - table of contents datasheet flash memory rev. 0.2 K9F2G08U0C 1.0 introduction ........... .............. .............. .............. .............. ............ ........... ........... .......... ......................................... 4 1.1 product list............................................................................................................... ............................................... 4 1.2 features ............................................................... ............................................................... .............................4 1.3 general description........................................................................................................ ......................................... 4 1.4 pin configuration (tsop1).................................................................................................. .................................... 5 1.4.1package dimensions ..... .............. .............. .............. .............. ........... ........... ........... .......... ................................. 5 1.5 pin configuration (fbga)................................................................................................... ..................................... 6 1.5.1package dimensions ..... .............. .............. .............. .............. ........... ........... ........... .......... ................................. 7 1.6 pin description ............................................................................................................ ............................................ 8 2.0 product introduction........................................................................................................... ........................... 9 2.1 absolute maximum ratings ...... ............................................................................................. .................................. 10 2.2 recommended operating conditions ..................... ...................................................................... .......................... 10 2.3 dc and operating characteristics(recommended operating c onditions otherwise noted.) . .............. ........... ......... 10 2.4 valid block................................................................................................................ ............................................... 11 2.5 ac test condition .......................................................................................................... ......................................... 11 2.6 capacitance(ta=25c, vcc= 3.3v, f=1.0mhz) .................................................................................. .................... 11 2.7 mode selection............................................................................................................. ........................................... 11 2.8 program / erase characteristics ............................................................... .........................................................12 2.9 ac timing characteristics for command / address / da ta input ............................................................... ............. 12 2.10 ac characteristics for operation................... ....................................................................... ................................. 13 3.0 nand flash technical notes ............ .............. .............. .............. .............. ........... ............ .......... ..................... 14 3.1 initial invalid block(s) ................................................................................................... ............................................ 14 3.2 identifying initial invalid blo ck(s) ....................................................................................... ...................................... 14 3.3 error in write or read operation .................... ....................................................................... ................................. 15 3.4 addressing for program operation ..................... ...................................................................... ............................... 17 4.0 system interface using ce don?t-care . .............. .............. .............. .............. .............. ........... ......... ........... 18 4.1 command latch cycle ..... .............. .............. .............. .............. ........... ........... ............ ......... .................................... 19 4.2 address latch cycle........................................................................................................ ........................................ 19 4.3 input data latch cycle ..................................................................................................... ....................................... 20 4.4* serial access cycle after read(cle=l, we=h, ale= l)........................................................................ ............... 20 4.5 status read cycle ......................................................................................................... ......................................... 21 4.6 read operation ............................................................................................................. .......................................... 21 4.7 read operation(intercepted by ce) .......................................................................................... .............................. 22 4.8 random data output in a page .............................................................................................. ............................... 23 4.9 page program operation..................................................................................................... .................................... 24 4.10 page program operation with rand om data input ............................................................................. .................. 25 4.11 copy-back program operation with random data in put ....................................................................... ............. 26 4.12 two- plane page program operat oin ............... .............. .............. .............. ........... ........... .......... ........................... 27 4.13 block erase operation..................................................................................................... ...................................... 28 4.14 read id operation......................................................................................................... ........................................ 28 5.0 device operation ........................................................................................................... ..................................... 31 5.1 page read.................................................................................................................. ............................................. 31 5.2 page program ............................................................................................................... .......................................... 33 5.3 copy-back program.......................................................................................................... ....................................... 34 5.4 read status................................................................................................................ ............................................. 35 5.5 read id .................................................................................................................... ............................................... 36 5.6 reset ...................................................................................................................... ................................................. 36 5.7 ready/busy ................................................................................................................. ........................................ 37 6.0 data protection & power up sequence........................................................................................... ......... 38 7.0 backward compatibility information............................................................................................. ............ 39 free datasheet http://www.datasheetlist.com/ - 4 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 1.0 introduction 1.1 product list 1.2 features 1.3 general description offered in 256mx8bit, the K9F2G08U0C is a 2g -bit nand flash memory with spare 64m-bi t. its nand cell provides the most cost-eff ective solution for the solid state application ma rket. a program operation can be performed in typical 250 s on the (2k+64)byte page and an erase operation can be per- formed in typical 2ms on a (128k+4k)byte block. data in the data register can be read out at 25 ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. the on-chip write controller automates al l program and erase functions including pulse repeti- tion, where required, and internal verification and margining of data. even the write-intensive systems can take advantage of t he K9F2G08U0C s extended reliability of 100k progra m/erase cycles by providing ec c(error correcting code) with r eal time mapping-out algorithm. the K9F2G08U0C is an optimum solution for large nonvolatile storage applications su ch as solid state file storage and other portable applications requiring non-volatility. part number vcc range organization pkg type K9F2G08U0C- s 2.7 ~ 3.6v x8 tsop1 K9F2G08U0C-h 2.7 ~ 3.6v x8 63 fbga ? voltage supply - 3.3v device(K9F2G08U0C): 2.70v ~ 3.60v ? organization - memory cell array : (256m + 8m) x 8bit - data register : (2k + 64) x 8bit ? automatic program and erase - page program : (2k + 64)byte - block erase : (128k + 4k)byte ? page read operation - page size : (2k + 64)byte - random read : 40 s(max.) - serial access : 25 ns(min.) ? fast write cycle time - page program time : 250 s(typ.) - block erase time : 2ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology -endurance & data retention : refor to the gualification report -ecc regnirement : 1 bit / 528bytes ? command driven operation ? unique id for copyright protection ? package : - K9F2G08U0C-scb0/sib0 : pb-free package 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - K9F2G08U0C-hcb0/hib0 : pb-free package 63 - ball fbga (9 x 11 / 0.8 mm pitch) free datasheet http://www.datasheetlist.com/ - 5 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 1.4 pin configuration (tsop1) K9F2G08U0C- s cb0/ s ib0 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c 1.4.1 package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 r 0.008 20.00 r 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 r 0.002 1.00 r 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 r 0.004 18.40 r 0.10 0~8 q 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () free datasheet http://www.datasheetlist.com/ - 6 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 1.5 pin configuration (fbga) K9F2G08U0C-hcb0/hib0 r/b /we /ce vss ale /wp /re cle nc nc nc nc vcc nc nc i/o0 i/o1 nc nc vcc i/o5 i/o7 vss i/o6 i/o4 i/o3 i/o2 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c 3456 1 2 a b c d g e f h top view free datasheet http://www.datasheetlist.com/ - 7 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 1.5.1 package dimensions 63-ball fbga (measured in millimeters) 9.00 0.10 #a1 side view top view 1.00(max.) 0.45 0.05 4321 a b c d g bottom view 11.00 0.10 63- ? 0.45 0.05 0.80 x7= 5.60 11.00 0.10 0.80 x 5= 4.00 0.80 0.25(min.) 0.10max b a 2.80 2.00 9.00 0.10 (datum b) (datum a) 0.20 m a b ? 0.80 0.80 x11= 8.80 0.80 x 9= 7.20 65 9.00 0.10 e f h 2.00 free datasheet http://www.datasheetlist.com/ - 8 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 1.6 pin description note : connect all vcc and v ss pins of each device to common power supply outputs. do not leave vcc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. re read enable the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the fall- ing edge of re which also increments the inter nal column address counter by one. we write enable the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent program/eras e protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r/b ready/busy output the r/b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completi on. it is an open drain output and does not float to high-z con- dition when the chip is deselect ed or when outputs are disabled. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. free datasheet http://www.datasheetlist.com/ - 9 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 2.0 product introduction nand flash memory has addresses multiplexed into 8 i/os. this scheme dramatically reduces pin counts and allows system upgrades to future densiti es by maintaining consist ency in system board design. command, address and dat a are all written through i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. some comm ands require one bus cycle. for example, reset command, status read command, etc. requ ire just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the othe r cycle for execution.. page read and page program need the same five address cycles fo llowing the required command input. in block erase operation, ho wever, only the three row address cycles are used. device operations are selected by writing specific commands into the command register. table 1 defines the specific commands of the k9g2g08u0c. [table 1] command sets note : 1) random data input/output can be executed in a page. 2) any command between 11h and 81h is prohibited except 70h/f1h and ffh. caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st cycle 2nd cycle acceptable command during busy read 00h 30h read for copy back 00h 35h read id 90h - reset ffh - o page program 80h 10h copy-back program 85h 10h two-plane page program (2) 80h---11h 81h---10h block erase 60h d0h random data input (1) 85h - random data output (1) 05h e0h read status 70h - o read status 2 f1h - o free datasheet http://www.datasheetlist.com/ - 10 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 2.1 absolute maximum ratings note : 1) minimum dc voltage is -0.6v on input/output pins. during tran sitions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data shee t. exposure to absolute maximum ra ting conditions for extended per iods may affect reliability. 2.2 recommended operating conditions (voltage reference to gnd, K9F2G08U0C-xcb0 : t a =0 to 70 c, K9F2G08U0C-xib0 : t a =-40 to 85 c) 2.3 dc and operating characteristics (recommended operating conditions otherwise noted.) note : 1) v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. 2) typical value is measured at vcc= 3.3v, t a =25 c. not 100% tested. parameter symbol rating unit voltage on any pin relative to vss v cc -0.6 to +4.6 v v in -0.6 to +4.6 v i/o -0.6 to vcc + 0.3 (< 4.6v) temperature under bias K9F2G08U0C-xcb0 t bias -10 to +125 c K9F2G08U0C-xib0 -40 to +125 storage temperature K9F2G08U0C-xcb0 t stg -65 to +150 c K9F2G08U0C-xib0 short circuit current i os 5 ma parameter symbol 3.3v unit min typ. max supply voltage v cc 2.7 3.3 3.6 v supply voltage v ss 000v parameter symbol test conditions 3.3v unit min typ max operating current page read with serial access i cc 1 trc= 25 ns ce =v il, i out =0ma -2035 ma program i cc 2- erase i cc 3- stand-by current(ttl) i sb 1ce =v ih , wp =0v/v cc --1 stand-by current(cmos) i sb 2ce =v cc -0.2, wp =0v/v cc -10 80 a input leakage current i li v in =0 to vcc(max) - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 input high voltage v ih (1) - 0.8xvcc - vcc+0.3 v input low voltage, all inputs v il (1) - -0.3 - 0.2xvcc output high voltage level v oh k9f2g08b0c: i oh= -100 a K9F2G08U0C: i oh =-400 a 2.4 - - output low voltage level v ol k9f2g08b0c: i ol= 100 a K9F2G08U0C: i ol =2.1ma --0.4 output low current(r/b )i ol (r/b ) k9f2g08b0c: v ol =0.1v K9F2G08U0C: v ol =0.4v 810 -ma free datasheet http://www.datasheetlist.com/ - 11 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 2.4 valid block note : 1) the device may include initial invalid blocks when first ship ped. additional invalid blocks may develop while being used. th e number of valid blocks is presented with both cases of invalid blocks considered . invalid blocks are defined as bl ocks that contain one or more bad bits. do not erase or pro gram factory-marked b ad blocks. refer to the attached technical notes for appropriate management of invalid blocks. 2) the 1st block, which is placed on 00h block address, is guar anteed to be a valid block up to 1k program/erase cycles with 1 bit/528byte ecc. 3) the number of valid block is on the basis of single pla ne operations, and this may be decreased with two plane operations. 2.5 ac test condition (K9F2G08U0C-xcb0 :ta=0 to 70 c, K9F2G08U0C-xib0:ta=-40 to 85 c, K9F2G08U0C: vcc=2.7v~3.6v unless otherwise noted) 2.6 capacitance (t a =25 c, v cc = 3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. 2.7 mode selection note : 1) x can be v il or v ih. 2) wp should be biased to cmos high or cmos low for standby. parameter symbol min typ. max unit K9F2G08U0C n vb 2,008 - 2,048 blocks parameter K9F2G08U0C input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load 1 ttl gate and cl=50pf item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf cle ale ce we re wp mode hll hx read mode command input l h l h x address input(5clock) hll hh write mode command input l h l h h address input(5clock) lll hh data input lllh x data output x x x x h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by free datasheet http://www.datasheetlist.com/ - 12 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 2.8 program / erase characteristics note : 1) typical value is measured at vcc=3.3v, t a =25 c. not 100% tested. 2) typical program time is defined as the time within which mo re than 50% of the whole pages are programmed at 3.3v vcc and 25 c temperature . 2.9 ac timing characteristics for command / address / data input note : 1) the transition of the corresponding c ontrol pins must occur only once while we is held low 2) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle parameter symbol min typ max unit program time t prog - 250 750 s dummy busy time for two-plane page program t dbsy - 2.5 3 s number of partial program cycles nop - - 4 cycles block erase time t bers - 2 10 ms parameter symbol min max unit cle setup time t cls (1) 12 -ns cle hold time t clh 5-ns ce setup time t cs (1) 20 - ns ce hold time t ch 5-ns we pulse width t wp 12 -ns ale setup time t als (1) 12 -ns ale hold time t alh 5- ns data setup time t ds (1) 12 -ns data hold time t dh 5-ns write cycle time t wc 25 -ns we high hold time t wh 10 - ns address to data loading time t adl (2) 100 - ns free datasheet http://www.datasheetlist.com/ - 13 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 2.10 ac characteristics for operation note : 1) if reset command(ffh) is written at ready state, the device goes into busy for maximum 5 s. parameter symbol min max unit data transfer from cell to register t r - 40 s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 12 -ns we high to busy t wb -100 ns read cycle time t rc 25 -ns re access time t rea -20ns ce access time t cea -25ns re high to output hi-z t rhz -100ns ce high to output hi-z t chz -30ns ce high to ale or cle don?t care t csd 10 -ns re high to output hold t rhoh 15 - ns ce high to output hold t coh 15 - ns re high hold time t reh 15 -ns output hi-z to re low t ir 0-ns re high to we low t rhw 100 - ns we high to re low t whr 60 - ns device resetting time(read/program/erase) t rst - 5/10/500 (1) s free datasheet http://www.datasheetlist.com/ - 14 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 3.0 nand flash technical notes 3.1 initial invalid block(s) [figure 1] flow chart to create initial invalid block table initial invalid blocks are defined as blocks that contain one or more initial invalid bit s whose reliability is not guaranteed by samsung. the information regarding the initial invalid bloc k(s) is called the initial invalid block inform ation. devices with initial invalid block(s) h ave the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invali d block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system design must be able to mask out the initial invalid block(s) via address mapping. the 1st block, which is placed on 00h block addres s, is guaranteed to be a valid block up to 1k program/erase cycles with 1bit /528byte ecc . 3.2 identifying initial invalid block(s) all device locations are erased(ffh) except locations where the initial invalid block(s) information is written prior to shippi ng. the initial invalid block(s) status is defined by the 1st byte in the spare area. samsung make s sure that either the 1st or 2nd page of every initial invali d block has non-ffh data at the column address of 2048. since the initial invalid block inform ation is also erasable in most cases, it is impossible to rec over the information once it has been erased. therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the foll owing suggested flow chart(figure 1). any in tentional erasure of the original initial invalid block information is pro- hibited. * check "ffh" at the column address 2048 start set block address = 0 check "ffh" increment block address last block ? end no yes yes create (or update) no initial of the 1st and 2nd page in the block invalid block(s) table free datasheet http://www.datasheetlist.com/ - 15 - datasheet flash memory rev. 0.2 K9F2G08U0C advance nand flash technical notes (continued) 3.3 error in write or read operation within its life time, additional invalid blocks may develop with nand flash memory. refer to the qualification report for the a ctual data.the following pos- sible failure modes should be considered to implement a highly reliable system. in t he case of status read failure after erase or program, block replace- ment should be done. because program status fail during a page pr ogram does not affect the data of the other pages in the same block, block replacement can be executed with a page-siz ed buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. in case of read, ecc must be employed. to improve the efficiency of me mory space, it is recommended that the read or verifica- tion failure due to single bit error be reclaimed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection program flow chart failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read single bit failure verify ecc -> ecc correction start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * free datasheet http://www.datasheetlist.com/ - 16 - datasheet flash memory rev. 0.2 K9F2G08U0C advance nand flash technical notes (continued) * step1 when an error happens in the nth page of the bloc k ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program to block ?a? by creating an ?invalid block? table or other appropriate scheme. erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes write 30h block replacement buffer memory of the controller. 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2 free datasheet http://www.datasheetlist.com/ - 17 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 3.4 addressing for program operation within a block, the pages must be programmed consecutively from the lsb(least significant bit) p age of the block to the msb(mos t significant bit) pages of the block. random page address programming is prohibited. in this case, the definition of lsb page is the lsb among the page s to be programmed. therefore, lsb doesn't need to be page 0. from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 : : : : free datasheet http://www.datasheetlist.com/ [figure 3] read operation with ce don?t-care. [figure 2] program operation with ce don?t-care. - 18 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 4.0 system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or serial access as shown below. the in ternal 2,112byte data registers are utilized as separate buffers for this operation and the system des ign gets more flexible. in addition, for voice or audio appli cations which use slow cycle time on the order of p -seconds, de-activating ce during the data-loading and serial access would pr ovide significant savings in power consumption. note : device i/o data address i/ox data in/out col. add1 col. add2 row add1 row add2 row add3 K9F2G08U0C i/o 0 ~ i/o 7 2,112byte a0~a7 a8~a11 a12~a19 a20~a27 a28 ce we t wp t ch t cs address(5cycles) 80h data input ce cle ale we data input ce don?t-care 10h t cea out t rea ce re i/o 0 ~ 7 i/ox | | | | | | | | | | | | address(5cycle) 00h ce cle ale we i/o x data output(serial access) ce don?t-care r/b t r re 30h | | | | | | free datasheet http://www.datasheetlist.com/ - 19 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 4.1 command latch cycle ce we cle ale command t cls t cs t clh t ch t wp t als t alh t ds t dh i/ox 4.2 address latch cycle ce we cle ale col. add1 t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t ds t dh t wp i/ox col. add2 row add1 row add2 t wc t wh t alh t als t ds t dh row add3 t alh t cls free datasheet http://www.datasheetlist.com/ - 20 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 4.3 input data latch cycle ce cle we din 0 din 1 din final ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp | | | i/ox | | | 4.4* serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t rhoh t rea t reh t rea t coh t rhz | | | | i/ox t chz t rhz note : transition is measured at r 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. trhoh starts to be valid when frequency is lower than 33mhz. free datasheet http://www.datasheetlist.com/ - 21 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 4.5 status read cycle ce we cle re status output t clr t clh t wp t ch t ds t dh t rea t ir t rhoh t coh t whr t cea t cls i/ox t chz t rhz t cs 70h/f1h 4.6 read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc | | | row add2 30h t clr i/ox row add3 t csd free datasheet http://www.datasheetlist.com/ - 22 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 4.7 read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h i/ox col. add1 col. add2 row add1 row add2 row add3 t c oh t clr t csd free datasheet http://www.datasheetlist.com/ - 23 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 4.8 random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t w b t ar t r t rr 30h 05h column address dout m dout m+1 i/ox col. add1 col. add2 row add1 row add2 col add1 col add2 row add3 t clr e0h t whr t rea t rc t rhw free datasheet http://www.datasheetlist.com/ - 24 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 4.9 page program operation ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc | | | | i/ox co.l add1 col. add2 row add1 row add2 row add3 t ad t whr note : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. free datasheet http://www.datasheetlist.com/ - 25 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 4.10 page program operation with random data input ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc | | | | 85h random data input command column address t wc din j din k serial input | | i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add3 | note : t adl t adl t whr tadl is h time from the we rising edge of final address cycle to the we rising edge of first data cycle. free datasheet http://www.datasheetlist.com/ - 26 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 4.11 copy-back program operation with random data input ce cle r/b we ale re 00h i/o x 85h column address row address i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc | busy t wb t r busy | 10h copy-back data input command 35h column address row address data 1 data n | | i/ox col add1 col add2 row add1 row add2 col add1 col add2 row add1 row add2 row add3 row add3 70h note : t adl t whr read status command tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. free datasheet http://www.datasheetlist.com/ - 27 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 4.12 two- plane page program operatoin 80h i/o 0 ~ 7 r/b 11h ex.) two-plane page program t dbsy address & data input 81h 10h address & data input 70h/f1h t prog col add1,2 & row add 1,2,3 2112 byte data ce cle r/b we ale re 80h din n din 11h m serial data input command column address program tdbsy twb twc command (dummy) din n 10h tprog twb i/o program confirm command (true) 81h 70h/f1h page row address i/ox 1 up to 2112 byte data serial input din m read status command t dbsy : typ. 2.5us max. 3us col add1 col add2 row add1 row add2 row add3 col add1 col add2 row add1 row add2 row add3 col add1,2 & row add 1,2,3 2112 byte data a 0 ~ a 11 : valid a 12 ~ a 17 : fixed ?low? a 18 : fixed ?low? a 19 ~ a 29 : fixed ?low? a 0 ~ a 11 : valid a 12 ~ a 17 : valid a 18 : fixed ?high? a 19 ~ a 29 : valid note: any command between 11h and 81h is prohibited except 70h and ffh. note twhr free datasheet http://www.datasheetlist.com/ - 28 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 4.13 block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc | auto block erase setup command i/ox row add1 row add2 row add3 t whr 4.14 read id operation ce cle we ale re 90h read id command maker code device code 00h ech t rea address 1cycle i/ox t ar device 4th cyc. code 3rd cyc. 5th cyc. device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle K9F2G08U0C dah 10h 15h 44h free datasheet http://www.datasheetlist.com/ - 29 - datasheet flash memory rev. 0.2 K9F2G08U0C advance id definition table 3rd id data 4th id data description 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte maker code device code internal chip number, cell type, num ber of simultaneously programmed pages, etc page size, block size,redundant area size, or ganization, serial access minimum plane number, plane size description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not support support 0 1 cache program not support support 0 1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 1kb 2kb 4kb 8kb 0 0 0 1 1 0 1 1 block size (w/o redundant area ) 64kb 128kb 256kb 512kb 0 0 0 1 1 0 1 1 redundant area size ( byte/512byte) 8 16 0 1 organization x8 x16 0 1 serial access minimum 50ns/30ns 25ns reserved reserved 0 1 0 1 0 0 1 1 free datasheet http://www.datasheetlist.com/ - 30 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 5th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (w/o redundant area) 64mb 128mb 256mb 512mb 1gb 2gb 4gb 8gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 reserved 0 0 0 free datasheet http://www.datasheetlist.com/ - 31 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 5.0 device operation [figure 4] read operation 5.1 page read page read is initiated by writing 00h-30h to the command register along with five address cycles. after initial power up, 00h c ommand is latched. there- fore only five address cycles and 30h command initiates that operation after initial power up. the 2,112 bytes of data within the selected page are trans- ferred to the data registers in less than 40 p s (t r ). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the consec utive sequential data by writing random data output command. t he column address of next data, which is going to be out, may be changed to the address which follows random data output command. random data out put can be operated multiple times regardless of how many times it is done in a page. address(5cycle) 00h col. add.1,2 & row add.1,2,3 data output(serial access) data field spare field ce cle ale r/b we re t 30h i/ox | | | | | | free datasheet http://www.datasheetlist.com/ [figure 5] random data output in a page - 32 - datasheet flash memory rev. 0.2 K9F2G08U0C advance address 00h data output r/b re t 30h address 05h e0h 5cycles 2cycles data output data field spare field data field spare field i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 free datasheet http://www.datasheetlist.com/ [figure 7] random data input in a page [figure 6] program & read status operation - 33 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 5.2 page program the device is programmed bas ically on a page basis, but it does allow multiple partial page programming of a word or consecutiv e bytes up to 2,112, in a single page program cycle. the number of consecutive partial pa ge programming operation within the same page without an interve ning erase operation must not exceed 4 times for a single page. the addressing shoul d be done in sequential order in a block. a page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded in to the data register, followed by a non-volatile programming p eriod where the loaded data is programmed into the appropriate cell. the serial data loading period begins by i nputting the serial data input command(80h) , followed by the five cycle address input s and then serial data loading. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). random da ta input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming process. writing 10h alone without previously entering t he serial data will not initiate the progr amming process. the internal write sta te controller automatically exe- cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the st atus register. the system controll er can detect the completion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. on ly the read status command and reset command are valid while progra m- ming is in progress. when the page program is complete, the write status bit(i/o 0) may be checked(figure 6). the internal writ e verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status command mode until an other valid command is written to the command register. 80h r/b address & data input i/o0 pass data 10h 70h fail t prog i/ox col. add.1,2 & row add.1,2,3 "0" "1" 80h r/b address & data input i/o0 pass 10h 70h fail t prog 85h address & data input i/ox col. add.1,2 & row add1,2,3 col. add.1,2 data data "0" "1" free datasheet http://www.datasheetlist.com/ [figure 9] page copy-back program operation with random data input [figure 8] page copy-back program operation - 34 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 5.3 copy-back program copy-back program with read for copy-back is configured to quick ly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. since the ti me-consuming re-loading cycles are removed, the system performance is improved. the be nefit is especially obvi- ous when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. co py-back operation is a sequential execution of read for copy-back and of copy-back program with the destination page address. a read operation with "3 5h" command and the address of the source page moves the whole 2,112-byte data into the internal data buffer. a bit error is checked by sequential reading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore copy-back pr ogram operation is initiated b y issuing page-copy data- input command (85h) with destination page address. actual progra mming operation begins after program confirm command (10h) is i ssued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system controlle r can detect the com- pletion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status r egister. when the copy-back program is complete, the write status bit(i/o 0) may be checked(figure 8 & figure 9). the command register remains in read status command mode until an other valid com- mand is written to the command register. during copy-back program, data modificati on is possible using random data input command (85h) as shown in figure 9. note : copy-back program operation is allowe d only within the same memory plane. "0" "1" 00h r/b add.(5cycles) i/o0 pass 85h 70h fail t prog add.(5cycles) t r source address destination address 35h 10h i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 00h r/b add.(5cycles) 85h 70h t prog add.(5cycles) t r source address destination address data 35h 10h 85h data add.(2cycles) there is no limitation for the number of repetition. i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 col. add.1,2 free datasheet http://www.datasheetlist.com/ - 35 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 5.4 read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. after writing 70h/f1h comm and to the command register, a read cycle outputs the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows t he system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for specific sta- tus register definitions and table 3 for specific f1h status re gister definitions. the command r egister remains in status read mode until further com- mands are issued to it. therefore, if the status register is read during a random read cycle, the read command(00h) should be g iven before starting read cycles. [table 2] read status register definition for 70h command note : i/os defined ?not use? are recommended to be masked out when read stat us is being executed. [table 3] read status 2 register definition for f1h command note : i/os defined ?not use? are recommended to be masked out when read stat us is being executed. i/o page program block erase read definition i/o 0 pass/fail pass/fail not use pass : "0" fail : "1" i/o 1 not use not use not use don?t -cared i/o 2 not use not use not use don?t -cared i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect protected : "0" not protected : "1" "1"otected i/o no. page program block erase read definition i/o 0 chip pass/fail chip pass/fail not use pass : "0" fail : "1" i/o 1 plane0 pass/fail plane0 pass/fail not use pass : "0" fail : "1" i/o 2 plane1 pass/fail plane1 pass/fail not use pass : "0" fail : "1" i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect protected : "0" not protected : "1" "1"otected free datasheet http://www.datasheetlist.com/ [figure 10] read id operation [figure 11] reset operation - 36 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 5.5 read id the device contains a product identificati on mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. five read cycles sequentially output the manufacturer code(ech), and the device code and 3rd, 4th, 5th cycle id respectively. the command regis ter remains in read id mode until further commands are issued to it. figure 10 shows the operation sequence. 5.6 reset the device offers a reset feature, executed by writing ffh to t he command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort these operations. the co ntents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait fo r the next command, and the status register is cleared to value c0h when wp is high. if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin changes to low for trst after the reset command is written. refer to figure 11 below. device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle K9F2G08U0C dah 10h 15h 44h after power-up after reset operation mode mode 00h command is latched waiting for next command ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea t whr t clr device 4th cyc. code ech 3rd cyc. 5th cyc. ffh i/o x r/b t rs free datasheet http://www.datasheetlist.com/ [figure 12] rp vs tr ,tf & rp vs ibusy - 37 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 5.7 ready/ busy the device has a r/b output that provides a hardware method of indicating the comp letion of a page program, erase and random read completion. the r / b pin is normally high but transitions to low after program or erase command is written to the command register or random read i s started after address loading. it returns to high when the internal controller has fi nished the operation. the pin is an open-drain driver thereby al lowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appr opriate value can be obtained with the fol- lowing reference chart(figure 12). its val ue can be determined by the following guidance. v cc r/b open drain output device gnd rp ibusy busy ready vcc voh tf tr vol c l 3.3v device - vol : 0.4v, voh : 2.4v tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 q c , c l = 50pf 1k 2k 3k 4k 100n 200n 2m 1m 50 tf 100 150 200 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maxi mum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + 6 i l = 3.2v 8ma + 6 i l free datasheet http://www.datasheetlist.com/ [figure 13] ac waveforms for power transition - 38 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 6.0 data protection & power up sequence the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 2v(3.3v device). wp pin provides hardware protection and is recommended to be kept at v il during power-up and power- down. a recovery time of minimum 1ms is required before internal circuit gets ready for any command sequences as shown in figure 13. the two step command sequence for program/erase prov ides additional software protection. v cc wp high | | we | | | ready/busy 5 ms max operation 1ms ~ 2.3v ~ 2.3v invalid don?t care don?t care free datasheet http://www.datasheetlist.com/ - 39 - datasheet flash memory rev. 0.2 K9F2G08U0C advance 7.0 backward compatibility information the below table shows key parameters which are different with prev ious product, so that the host c ould use make or modify its f irmware without misun- derstanding of compatibility. but the below table don?t have all the difference with previous product, but only key parameters? changing which can be defined to have an effect on developing nand firmware or hardware. previous generation product current generation device part id k9f2g08u0b K9F2G08U0C features & operations 1. tr: 25us / tprog(200us typ, 700us max) ters(1.5ms typ, 10ms max) 2. trc/twc: 25ns 3. 2 plane program: support 4. 2plane copy-back program: support 5. 2plane erase: support 6. edo: support 1. tr: 40 us / tprog(250us typ, 750us max) ters(2ms typ, 10ms max) 2. trc/twc: 25 ns 3. 2 plane program: support 4. 2plane copy-back program: n/a 5. 2plane erase: n/a 6. edo: n/a ac & dc parameters 1. icc1 : 15ma(typ)/ 30ma(max) 2. icc2 : 15ma(typ)/ 30ma(max) 3. icc3 : 15ma(typ)/ 30ma(max) 1. icc1 : 20ma(typ)/ 35ma(max) 2. icc2 : 20ma(typ)/ 35ma(max) 3. icc3 : 20ma(typ)/ 35ma(max) technical notes free datasheet http://www.datasheetlist.com/ |
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